Recently CSPs (Chip Size Packages), which are semiconductor devices packaged with effectively the same outer dimensions as those of semiconductor chips, have been proposed following a demand for high integration and miniaturization of semiconductor devices used in electronic equipment.
Among such CSPs, WCSPs (Waferlevel CSPs) which are CSPs that are divided into pieces by dicing after the process of forming the external terminals has been completed while still in wafer form, are focused on with a view to reducing production costs (for example, see patent document 1).
WCSPs have a construction having electrodes and external terminals on a semiconductor chip electronically connected to each other via a wiring layer (also called a rewiring layer) which repositions external terminals at desired positions, and has better flexibility of wiring design.
Furthermore, recently with a view to achieving high performance WCSPs, there has been a construction which amplifies the inductance of a WCSP by having a coil built-in as an induction element (also called an inductor) in the WCSP, (for example, see patent document 2).
There are prior art publications as follows:
(1) Japanese Unexamined Patent Publication No. 2002-57292
(2) Japanese Unexamined Patent Publication No. 2002-164468
However, when a spiral coil is mounted on a semiconductor chip for example, the windings of the coil have to be increased further in order to achieve an increase in the inductance of the coil.
However, the proportion of the coil which occupies the surface of the semiconductor chip (that is, the area occupied by the coil) increases by increasing the windings of the coil.
As a result, because enlargement of the semiconductor chip becomes unavoidable, there is the concern that a reduction in the number of semiconductor chips formed from a single wafer leads to a decrease in production efficiency.